my project designing a vending machine that sells a candy for 40 cent. it accept olny 5 cent(N) and 10 cent (D). and the candy i wrote this code for this but i couldn't write a testbench to see waveform Can you help me please
library ieee;
use ieee.std_logic_1164.all;

entity vending_machine is
port (
CLK, RESET: in std_logic;
N, D: in std_logic;
output: out std_logic;
change: out std_logic_vector(5 downto 0)
);
end vending_machine;

architecture process_3 of vending_machine is
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
signal state, next_state: state_type;

begin
process (CLK, RESET)
begin
if (RESET = '1') then
state <= s0;
elsif (rising_edge(CLK)) then
state <= next_state;
end if;
end process;

process (state, N, D)
begin
case state is
when s0 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "000000";
elsif N = '0' and D = '1' then
next_state <= s1;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
next_state <= s2;
output <= '0';
change <= "000000";
end if;

when s1 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "000101";
elsif N = '0' and D = '1' then
next_state <= s2;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
next_state <= s3;
output <= '0';
change <= "000000";
end if;

when s2 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "001010";
elsif N = '0' and D = '1' then
next_state <= s3;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
next_state <= s4;
output <= '0';
change <= "000000";
end if;

when s3 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "001111";
elsif N = '0' and D = '1' then
next_state <= s4;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
next_state <= s5;
output <= '0';
change <= "000000";
end if;

when s4 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "010100";
elsif N = '0' and D = '1' then
next_state <= s5;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
next_state <= s6;
output <= '0';
change <= "000000";
end if;

when s5 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "011001";
elsif N = '0' and D = '1' then
next_state <= s6;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
next_state <= s7;
output <= '0';
change <= "000000";
end if;

when s6 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "011110";
elsif N = '0' and D = '1' then
next_state <= s7;
output <= '0';
change <= "000000";
elsif N = '1' and D = '0' then
if RESET = '1' then
next_state <= s0;
output <= '1';
change <= "000000";
else
next_state <= s8;
output <= '1';
change <= "000000";
end if;
end if;

when s7 =>
if N = '0' and D = '0' then
next_state <= s0;
output <= '0';
change <= "100011";
elsif N = '0' and D = '1' then
if RESET = '1' then
next_state <= s0;
output <= '1';
change <= "000101";
else
next_state <= s9;
output <= '1';
change <= "000101";
end if;
elsif N = '1' and D = '0' then
if RESET = '1' then
next_state <= s0;
output <= '1';
change <= "000000";
else
next_state <= s9;
output <= '1';
change <= "000000";
end if;
end if;
when s8 =>
if N = '0' and D = '0' then
if RESET = '1' then
next_state <= s0;
output <= '1';
change <= "000000";
else
next_state <= s8;
output <= '1';
change <= "000000";
end if;
end if;

when s9 =>
if RESET = '1' then
next_state <= s0;
output <= '1';
change <= "000101";
else
next_state <= s9;
output <= '0';
change <= "000000";
end if;

when others =>
next_state <= s0;
output <= '0';
change <= "000000";
end case;
end process;

end architecture process_3;

--- MBSE BBS v1.0.8 (Linux-x86_64)
* Origin: ---:- FTN<->UseNet Gate -:--- (3:633/280.2@fidonet)

On Thursday, June 15, 2023 at 2:15:19=E2=80=AFPM UTC-4, Esma wrote:

my project designing a vending machine that sells a candy for 40 cent. it=

accept olny 5 cent(N) and 10 cent (D). and the candy i wrote this code for=
this but i couldn't write a testbench to see waveform Can you help me plea= se=20

library ieee;=20
use ieee.std_logic_1164.all;=20
=20
entity vending_machine is=20
port (=20
CLK, RESET: in std_logic;=20
N, D: in std_logic;=20
output: out std_logic;=20
change: out std_logic_vector(5 downto 0)=20
);=20
end vending_machine;=20
=20
architecture process_3 of vending_machine is=20
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);=20
signal state, next_state: state_type;=20
=20
begin=20
process (CLK, RESET)=20
begin=20
if (RESET =3D '1') then=20
state <=3D s0;=20
elsif (rising_edge(CLK)) then=20
state <=3D next_state;=20
end if;=20
end process;=20
=20
process (state, N, D)=20
begin=20
case state is=20
when s0 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s1;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
next_state <=3D s2;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when s1 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "000101";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s2;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
next_state <=3D s3;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when s2 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "001010";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s3;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
next_state <=3D s4;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when s3 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "001111";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s4;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
next_state <=3D s5;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when s4 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "010100";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s5;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
next_state <=3D s6;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when s5 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "011001";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s6;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
next_state <=3D s7;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when s6 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "011110";=20
elsif N =3D '0' and D =3D '1' then=20
next_state <=3D s7;=20
output <=3D '0';=20
change <=3D "000000";=20
elsif N =3D '1' and D =3D '0' then=20
if RESET =3D '1' then=20
next_state <=3D s0;=20
output <=3D '1';=20
change <=3D "000000";=20
else=20
next_state <=3D s8;=20
output <=3D '1';=20
change <=3D "000000";=20
end if;=20
end if;=20
=20
when s7 =3D>=20
if N =3D '0' and D =3D '0' then=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "100011";=20
elsif N =3D '0' and D =3D '1' then=20
if RESET =3D '1' then=20
next_state <=3D s0;=20
output <=3D '1';=20
change <=3D "000101";=20
else=20
next_state <=3D s9;=20
output <=3D '1';=20
change <=3D "000101";=20
end if;=20
elsif N =3D '1' and D =3D '0' then=20
if RESET =3D '1' then=20
next_state <=3D s0;=20
output <=3D '1';=20
change <=3D "000000";=20
else=20
next_state <=3D s9;=20
output <=3D '1';=20
change <=3D "000000";=20
end if;=20
end if;=20
when s8 =3D>=20
if N =3D '0' and D =3D '0' then=20
if RESET =3D '1' then=20
next_state <=3D s0;=20
output <=3D '1';=20
change <=3D "000000";=20
else=20
next_state <=3D s8;=20
output <=3D '1';=20
change <=3D "000000";=20
end if;=20
end if;=20
=20
when s9 =3D>=20
if RESET =3D '1' then=20
next_state <=3D s0;=20
output <=3D '1';=20
change <=3D "000101";=20
else=20
next_state <=3D s9;=20
output <=3D '0';=20
change <=3D "000000";=20
end if;=20
=20
when others =3D>=20
next_state <=3D s0;=20
output <=3D '0';=20
change <=3D "000000";=20
end case;=20
end process;=20
=20
end architecture process_3;

The bit that is important in the test bench is this:=20

entity vending_machine is
port (
CLK, RESET: in std_logic;
N, D: in std_logic;
output: out std_logic;
change: out std_logic_vector(5 downto 0)
);
end vending_machine;

You need to treat your design as a component in the test bench. Write code=
to drive the clock, the N and the D inputs as you choose. You can examine=
the outputs manually in the simulator, or, if you wish to analyze the desi=
gn carefully, you can write code to verify the outputs automatically. The = statement to assist with this is:=20

assert(exp);=20

Where exp is an expression that should evaluate to TRUE. If not, the asser=
t statement will print to the simulation output. You can combine assert wi=
th report to give a specific text output indicating exactly what is wrong, = including the value of the thing being tested.=20

--=20

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

--- MBSE BBS v1.0.8 (Linux-x86_64)
* Origin: ---:- FTN<->UseNet Gate -:--- (3:633/280.2@fidonet)