We're designing a little pulse generator and want to include a user-programmable trigger divisor, for pulse picking or whatever. At
least 150 MHz input would be good, more obviously better.
That got me to thinking about how to do a max-frequency 32-bit divider
in an Efinix T20 FPGA.
Here's my attempt:
https://www.dropbox.com/scl/fi/2uxfr2ar2sk1w2q4gy2if/Fast_Trig_Divider.jpg?rlkey=pab07rczg8i5t23gxp7a43zrn&raw=1
The idea is to use the counter fast-carry chain as the terminal count
detector. The added flop resynchronizes that and arguably speeds
things up.
This actually divides by 1-K, if you think of K as a negative number.
I think the Efinix chips like to do things in 18-bit chunks.
How's this look? Any other ideas?
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
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