john larkin <jl@glen--canyon.com>wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20
FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS >frequency synthesizer. We use a PLL inside the FPGA to spin up a 204
MHz clock for the 32-bit phase accumulator. The sine lookup is 4K
points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
john larkin <jl@glen--canyon.com>wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20
FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS >>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204
MHz clock for the 32-bit phase accumulator. The sine lookup is 4K
points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
john larkin <jl@glen--canyon.com>wrote:
On Thu, 23 Oct 2025 07:45:48 GMT, Jan Panteltje <alien@comet.invalid>wrote:
john larkin <jl@glen--canyon.com>wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS >>>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204
MHz clock for the 32-bit phase accumulator. The sine lookup is 4K
points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
If you program high drive strength, that T20 is pretty fierce...
https://www.dropbox.com/scl/fi/r97plmw3yvls3kgo0liy1/trion_drive_strength.pdf?rlkey=c3evk5zn7amn9ejx2dbtywter&dl=0
Well, that's what the IBIS model says.
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS >>>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204
MHz clock for the 32-bit phase accumulator. The sine lookup is 4K
points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS >>>>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for
me as a DIYer. Here's mouser's offering for the geniuses in our midst,
with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >fabrication became trivial thanks to the trimming technology of modern >lasers? Is the price of precision resistors still a factor?
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern
lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS >>>>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for
me as a DIYer. Here's mouser's offering for the geniuses in our midst,
with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >fabrication became trivial thanks to the trimming technology of modern >lasers? Is the price of precision resistors still a factor?
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>> frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K
points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>> me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for
me as a DIYer. Here's mouser's offering for the geniuses in our midst,
with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern
lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
On Thu, 23 Oct 2025 16:54:31 -0000 (UTC), "Don" <g@crcomp.net> wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for
me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>fabrication became trivial thanks to the trimming technology of modern >>lasers? Is the price of precision resistors still a factor?
I figured that using 1% resistors, this sort of dac would be about
monotonic at 6 bits. Six bits makes a pretty decent looking sine wave,
which filters/interpolates into a low jitter clock.
https://www.dropbox.com/scl/fi/n12quxajp59egahv1b48i/DDS_1KHz.jpg?rlkey=8w0tlr3h1rxeif3byepzub947&raw=1
R-2R made from discretes would use twice as many resistors.
The 204 MHz phase accumulator clock has 5 ns p-p jitter. Adding this
stuff improves jitter about 20:1.
It will need a fast comparator to make the sine into a cmos level
clock to feed back into the FPGA. An LVDS line receiver can do that.
Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>>> frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K
points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>> me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for
me as a DIYer. Here's mouser's offering for the geniuses in our midst,
with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>> fabrication became trivial thanks to the trimming technology of modern
lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic
outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors
in series with each of these outputs should be decreased by whatever you >measure that output resistance to be, otherwise the resistance ratio
isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >(which are not quite the same), measured on a typical chip, at room >temperature, so that it is usually at least roughly correct, rather than >systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the
error of 1% resistor tolerances, so it makes sense to fix that before >worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of
binary weighted resistor DACs.
john larkin <jl@glen--canyon.com>wrote:
On Thu, 23 Oct 2025 11:46:18 -0700, john larkin <jl@glen--canyon.com>wrote:
On Thu, 23 Oct 2025 16:54:31 -0000 (UTC), "Don" <g@crcomp.net> wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>>>frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>>me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for >>>me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>>fabrication became trivial thanks to the trimming technology of modern >>>lasers? Is the price of precision resistors still a factor?
I figured that using 1% resistors, this sort of dac would be about >>monotonic at 6 bits. Six bits makes a pretty decent looking sine wave, >>which filters/interpolates into a low jitter clock.
https://www.dropbox.com/scl/fi/n12quxajp59egahv1b48i/DDS_1KHz.jpg?rlkey=8w0tlr3h1rxeif3byepzub947&raw=1
R-2R made from discretes would use twice as many resistors.
The 204 MHz phase accumulator clock has 5 ns p-p jitter. Adding this
stuff improves jitter about 20:1.
It will need a fast comparator to make the sine into a cmos level
clock to feed back into the FPGA. An LVDS line receiver can do that.
Or stuff it into a differential input of the FPGA.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
Jan Panteltje <alien@comet.invalid>wrote:Oops, link:
FPGA_board_with_25MHz_VCXO_locked_to_rubidium_10MHz_reference_IMG_3724.GIF
It is worth fixing it for R-2R and also for at least a few msbs of
binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>>>> frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>>> me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603
resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for >>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>> converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>>> fabrication became trivial thanks to the trimming technology of modern >>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic
outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors
in series with each of these outputs should be decreased by whatever you
measure that output resistance to be, otherwise the resistance ratio
isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS
(which are not quite the same), measured on a typical chip, at room
temperature, so that it is usually at least roughly correct, rather than
systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the
error of 1% resistor tolerances, so it makes sense to fix that before
worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of
binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
On 10/24/25 08:56, Jan Panteltje wrote:
Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>>>>> frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>>>> me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>> resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for >>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>> converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of >>>>> precision resistors within its ladder network, making its design >>>>> both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>>>> fabrication became trivial thanks to the trimming technology of modern >>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic
outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors
in series with each of these outputs should be decreased by whatever you >>> measure that output resistance to be, otherwise the resistance ratio
isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS
(which are not quite the same), measured on a typical chip, at room
temperature, so that it is usually at least roughly correct, rather than >>> systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the
error of 1% resistor tolerances, so it makes sense to fix that before
worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of
binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
you can probably get it from the IBIS model
john larkin <jl@glen--canyon.com>wrote:
On Fri, 24 Oct 2025 13:40:25 +0200, Lasse Langwadt <llc@fonz.dk>wrote:
On 10/24/25 08:56, Jan Panteltje wrote:
Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>>>>
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>> resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for >>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>> converter has an analogue output voltage which is the weighted >>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>> precision resistors within its ladder network, making its design >>>>>> both expensive and impractical for most DAC's requiring lower >>>>>> levels of resolution.
Discussions in this group left me with the impression precision resistor >>>>>> fabrication became trivial thanks to the trimming technology of modern >>>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic
outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>> in series with each of these outputs should be decreased by whatever you >>>> measure that output resistance to be, otherwise the resistance ratio
isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>> (which are not quite the same), measured on a typical chip, at room
temperature, so that it is usually at least roughly correct, rather than >>>> systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the
error of 1% resistor tolerances, so it makes sense to fix that before
worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of
binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
Use Ohm's Law!
you can probably get it from the IBIS model
This is the IBIS of one gpio pin of the efinix T20.
https://www.dropbox.com/scl/fi/r97plmw3yvls3kgo0liy1/trion_drive_strength.pdf?rlkey=c3evk5zn7amn9ejx2dbtywter&dl=0
That's pullup to 3.3 volts, the pfet side.
You can see a small glitch at the midpoint of this sine wave
https://www.dropbox.com/scl/fi/n12quxajp59egahv1b48i/DDS_1KHz.jpg?rlkey=8w0tlr3h1rxeif3byepzub947&dl=0
which is the classic dac MSB crossover error. It's not enough to
matter, but I might tweak the first resistor to beautify that.
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote:
Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>>>
We often need programmable clocks so I added a few parts to make a DDS >>>>>>>> frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>>>> me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>> resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for >>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>> converter has an analogue output voltage which is the weighted
sum of the individual inputs. Thus it requires a large range of
precision resistors within its ladder network, making its design >>>>> both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>>>> fabrication became trivial thanks to the trimming technology of modern >>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic >>>outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>in series with each of these outputs should be decreased by whatever you >>>measure that output resistance to be, otherwise the resistance ratio >>>isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>(which are not quite the same), measured on a typical chip, at room >>>temperature, so that it is usually at least roughly correct, rather than >>>systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>error of 1% resistor tolerances, so it makes sense to fix that before >>>worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of >>>binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>>Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>>>>
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>>>> at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>> resistors that we have in stock.
Also, the ability to adjust assembled resistor values works better for >>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>> converter has an analogue output voltage which is the weighted >>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>> precision resistors within its ladder network, making its design >>>>>> both expensive and impractical for most DAC's requiring lower
levels of resolution.
Discussions in this group left me with the impression precision resistor >>>>>> fabrication became trivial thanks to the trimming technology of modern >>>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic >>>>outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>in series with each of these outputs should be decreased by whatever you >>>>measure that output resistance to be, otherwise the resistance ratio >>>>isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>>(which are not quite the same), measured on a typical chip, at room >>>>temperature, so that it is usually at least roughly correct, rather than >>>>systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>>error of 1% resistor tolerances, so it makes sense to fix that before >>>>worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of >>>>binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
Yes, that should work.
But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between.
But as a simple rule it should work.
Now people here were talking about that IBIS model.
If I ever get spice working on my computers (Raspberries these days) ....
Old spice version could still be running in wine in Linux on old PC upstairs. >For some reason I do not need Spice except in food.
On Sun, 26 Oct 2025 08:10:08 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote:
Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>>> resistors that we have in stock.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html >>>>>>>>
Also, the ability to adjust assembled resistor values works better for >>>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>>> converter has an analogue output voltage which is the weighted >>>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>>> precision resistors within its ladder network, making its design >>>>>>> both expensive and impractical for most DAC's requiring lower >>>>>>> levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern >>>>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic
outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>> in series with each of these outputs should be decreased by whatever you >>>>> measure that output resistance to be, otherwise the resistance ratio >>>>> isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>>> (which are not quite the same), measured on a typical chip, at room
temperature, so that it is usually at least roughly correct, rather than >>>>> systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>>> error of 1% resistor tolerances, so it makes sense to fix that before >>>>> worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of
binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
Yes, that should work.
But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between.
But as a simple rule it should work.
Now people here were talking about that IBIS model.
If I ever get spice working on my computers (Raspberries these days) ....
Old spice version could still be running in wine in Linux on old PC upstairs.
For some reason I do not need Spice except in food.
Spice is great for playing with ideas. We are developing a series of resistor-inductor simulators, RL dummy loads, that were invented by
fiddling with Spice. They work but I still don't understand them.
On 27/10/2025 1:56 am, john larkin wrote:
On Sun, 26 Oct 2025 08:10:08 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>>>> Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
The MSB actually sees 500 ohms.john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20
FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204
MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that. >>>>>>>>>
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>>>> resistors that we have in stock.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html >>>>>>>>>
Also, the ability to adjust assembled resistor values works better for >>>>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>>>> converter has an analogue output voltage which is the weighted >>>>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>>>> precision resistors within its ladder network, making its design >>>>>>>> both expensive and impractical for most DAC's requiring lower >>>>>>>> levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern >>>>>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic >>>>>> outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>>> in series with each of these outputs should be decreased by whatever you >>>>>> measure that output resistance to be, otherwise the resistance ratio >>>>>> isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>>>> (which are not quite the same), measured on a typical chip, at room >>>>>> temperature, so that it is usually at least roughly correct, rather than >>>>>> systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>>>> error of 1% resistor tolerances, so it makes sense to fix that before >>>>>> worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of >>>>>> binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
Yes, that should work.
But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between.
But as a simple rule it should work.
Now people here were talking about that IBIS model.
If I ever get spice working on my computers (Raspberries these days) .... >>> Old spice version could still be running in wine in Linux on old PC upstairs.
For some reason I do not need Spice except in food.
Spice is great for playing with ideas. We are developing a series of
resistor-inductor simulators, RL dummy loads, that were invented by
fiddling with Spice. They work but I still don't understand them.
That's risky. Spice isn't great on finding potential parasitic oscillations.
On Mon, 27 Oct 2025 03:19:45 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 27/10/2025 1:56 am, john larkin wrote:
On Sun, 26 Oct 2025 08:10:08 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>>>>> Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
The MSB actually sees 500 ohms.john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20
FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204
MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that. >>>>>>>>>>
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>>>>> resistors that we have in stock.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html >>>>>>>>>>
Also, the ability to adjust assembled resistor values works better for
me as a DIYer. Here's mouser's offering for the geniuses in our midst,
with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue
converter has an analogue output voltage which is the weighted >>>>>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>>>>> precision resistors within its ladder network, making its design
both expensive and impractical for most DAC's requiring lower >>>>>>>>> levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern
lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic >>>>>>> outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>>>> in series with each of these outputs should be decreased by whatever you
measure that output resistance to be, otherwise the resistance ratio >>>>>>> isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>>>>> (which are not quite the same), measured on a typical chip, at room >>>>>>> temperature, so that it is usually at least roughly correct, rather than
systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>>>>> error of 1% resistor tolerances, so it makes sense to fix that before >>>>>>> worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of >>>>>>> binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
Yes, that should work.
But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between.
But as a simple rule it should work.
Now people here were talking about that IBIS model.
If I ever get spice working on my computers (Raspberries these days) .... >>>> Old spice version could still be running in wine in Linux on old PC upstairs.
For some reason I do not need Spice except in food.
Spice is great for playing with ideas. We are developing a series of
resistor-inductor simulators, RL dummy loads, that were invented by
fiddling with Spice. They work but I still don't understand them.
That's risky. Spice isn't great on finding potential parasitic oscillations.
Differential equations and control theory aren't either.
A little practical experience can supplement a Spice sim. Spice
doesn't punch out gates if the voltage is too high, and Spice
transistor models don't include wirebond inductance.
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>>>Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>>> resistors that we have in stock.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html >>>>>>>>
Also, the ability to adjust assembled resistor values works better for >>>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>>> converter has an analogue output voltage which is the weighted >>>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>>> precision resistors within its ladder network, making its design >>>>>>> both expensive and impractical for most DAC's requiring lower >>>>>>> levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern >>>>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic >>>>>outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>>in series with each of these outputs should be decreased by whatever you >>>>>measure that output resistance to be, otherwise the resistance ratio >>>>>isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>>>(which are not quite the same), measured on a typical chip, at room >>>>>temperature, so that it is usually at least roughly correct, rather than >>>>>systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>>>error of 1% resistor tolerances, so it makes sense to fix that before >>>>>worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of >>>>>binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
Yes, that should work.
But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between.
But as a simple rule it should work.
Well, that gives static behaviour. Performing measurements at
multiple points one can get reasonable approximatin to V-I curve.
When building a DAC one want most resistance in external
resistors, so few points should be enough (one probably gets
more error due to variation in devices than due to nonlinearity).
Now people here were talking about that IBIS model.
If I ever get spice working on my computers (Raspberries these days) ....
On PC Linux Spice-NG compiles fine from sources. I did not try
to compile it on Raspberry Pi, but IME problems with compilation
on Raspberry Pi are rare, so I expect this to work.
OTOH Spice-NG can not read LTSpice file which folks here tend to
post. And Spice-NG comes with no device parameters. Parameters
for Fairchild 2N3904 and 1N4148 are in datasheet, so one can use
them. For handful of other devices I was able to find parmeters
on the net. But apparently, for most devices manufacturers
consider Spice paremterts as a secret. So due to lack of
device data Spice-NG can not be used for accurate simulation
(unless somebody can infer parameters from measurements or
have some other way to get them).
Concerning IBIS models, text that you linked in other post
clamis that the models are plain text with well-described
format. If true, one should be able to extract/interpolate
various curves from model data with rather simple ad-hoc
tool, without need for Spice.
BTW: I tried to use Spice-NG to simulate detector using 1N4148.
However, results I obtained look too good: according to Spice-NG
such detector should work for signals at few millivolt level and
well above 1GHz. My detectort was lightly loaded (1M resistor
+ filtering capacitor as a load) and low bandwidth. But if
1N4148 really works so well as Spice-NG claims, then people
using Shottky or germanium diodes in similar detectors are
overdoing it.
Old spice version could still be running in wine in Linux on old PC upstairs.
For some reason I do not need Spice except in food.
Concerning Raspberry Pi, currently Chinese mini-PC is cheaper
than Raspberry Pi powerful enough to serve as a main computer.
I recently bought a few cheap Orange Pi-s and Milkv Duo-s.
But they are low end machines. Would be reasonably powerful
as desktop/server in 2000 (or maybe in 1999, clock freqency was
increasing fast in those years), but not now. I am using
Orange Pi-s to check that my software compiles fine on ARM.
I have Milkv Mars, which is slightly more powerful than Milkv Duo S,
I use it to test that my software compiles fine on Risc-V.
But otherwise those boards are useful as a way to control electronics
via Ethernet
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>>>Chris Jones <lugnut808@spam.yahoo.com>wrote:
On 24/10/2025 4:20 am, Jan Panteltje wrote:
"Don" <g@crcomp.net>wrote:
john larkin wrote:
Jan Panteltje wrote:
john larkin wrote:
We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it.
We often need programmable clocks so I added a few parts to make a DDS
frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>>> points and the "dac" is six resistors.
This lowpass filter is tacky, but it all works. At 50 MHz, the jitter
is a few hundred ps p-p, and that looks mostly like amplitude noise to
me.
https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0
The FPGA 1.2v core supply uses about 30 mA total when this is running
at 50 MHz out.
Nice, 250 Ohm is a big load, good the FPGA can handle that.
The MSB actually sees 500 ohms.
One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>>> resistors that we have in stock.
I was using R2R for video:
https://www.electronics-tutorials.ws/combination/r-2r-dac.html >>>>>>>>
Also, the ability to adjust assembled resistor values works better for >>>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>>> with the foresight to always choose the correct component:
<https://www.mouser.com/c/passive-components/resistors/?circuit%20type=R%2F2R%20Ladder>
Jan's cited tutorial says:
Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>>> converter has an analogue output voltage which is the weighted >>>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>>> precision resistors within its ladder network, making its design >>>>>>> both expensive and impractical for most DAC's requiring lower >>>>>>> levels of resolution.
Discussions in this group left me with the impression precision resistor
fabrication became trivial thanks to the trimming technology of modern >>>>>>> lasers? Is the price of precision resistors still a factor?
In the case of R2R you can use resistors from one batch and that may have less spreading in values
No precision resistors needed.
(2R is then 2 1R resistors in series).
You don't want them the same though: The MOSFETS of the CMOS logic >>>>>outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>>in series with each of these outputs should be decreased by whatever you >>>>>measure that output resistance to be, otherwise the resistance ratio >>>>>isn't 1:2 in the R-2R network, and the DNL will be poor.
You could use the average of the on-resistance of the NMOS and the PMOS >>>>>(which are not quite the same), measured on a typical chip, at room >>>>>temperature, so that it is usually at least roughly correct, rather than >>>>>systematically and always wrong.
The MOSFET on-resistance is usually a more important effect than the >>>>>error of 1% resistor tolerances, so it makes sense to fix that before >>>>>worrying about selecting resistors from the same batch.
It is worth fixing it for R-2R and also for at least a few msbs of >>>>>binary weighted resistor DACs.
How would you go about measuring MOSFET on resistance?
For logic MOSFETS in IC-s I just used a multimeter. For power
MOSFETS I used "two meter" method: resitor to limit current to
reasonable range, ammeter to measure current, voltmeter to
measure voltage drop on the MOSFET. Actually, I had extrea
voltmeter to measure gate voltage.
Yes, that should work.
But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between.
But as a simple rule it should work.
Well, that gives static behaviour. Performing measurements at
multiple points one can get reasonable approximatin to V-I curve.
When building a DAC one want most resistance in external
resistors, so few points should be enough (one probably gets
more error due to variation in devices than due to nonlinearity).
antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>antispam@fricas.org (Waldek Hebisch)wrote:
In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote: >>>>>antispam@fricas.org (Waldek Hebisch)wrote:
Old spice version could still be running in wine in Linux on old PC upstairs.In sci.electronics.design Jan Panteltje <alien@comet.invalid> wrote:
For some reason I do not need Spice except in food.
Concerning Raspberry Pi, currently Chinese mini-PC is cheaper
than Raspberry Pi powerful enough to serve as a main computer.
Important thing for me is the I/O, Raspberry GPIO is sort of standardized
I have now 5 Raspberry Pies, 3 on 24/7 on a UPS.
One upstairs in the window that drives a big dot matrix display that can be seen from far away saying 'Free Palestine support
at 2 state solution'
It scrolls over 3 lines and flashes:-)
If display has sane control, then simple 8 pin micro should be
enough. Blue Pill certainly could do this.
Old picture:
https://panteltje.nl/pub/rtl_sdr_dump1090_via_FDS132_matrix_display_Raspberry_Pi_driver_IMG_4149.JPG
Raspberry number 5 is an old one and is backup.
I post this from a Pi4 8 GB with the Usenet newsreader I wrote.
Use it for all internet related things.
Fast as lightning, had to add a 4 second delay to be able to switch virtual desktop (nine virtual desktops in use)
fast enough before Chromium started by mouse click.
All sort of 'Hats' on some Raspies, compass, air pressure, IR camera interface,
One raspberry Pi4 4 GB records 6 security cameras, radiation, air traffic, plays background music, records audio,
A 8 TB Toshiba USB harddisc is connected to each PI4.
And there are 2 USB RTL_SDR sticks connected, one now records wireless data from the outside weather station, temperature,
humidity, also recorded 24/7,
the other one uses dump1090 for air traffic, or my spectrum analyzer.
https://panteltje.nl/pub/xpsa-0.7.gif
https://panteltje.nl/pub/boats_and_planes.gif
https://panteltje.nl/pub/xgpspc_5_planes.gif
And then there is the Ethernet interface, 3 gas sensors I designed are running 24/7 and are recorded, use POE,
LED lights in the room, can even function as disco lights controlled by playing music,
And the USB interface, SDcard reader, and for internet a Huawei 4G USB modem.
For 'on the road' I have a Samsung laptop running Ubuntu that I can put that Huawei 4G stick in and then am online in most of
Europe.
A Raspberry Pi 4 plus SDcard is below 100 Euro (even below 100 USD :-)
https://www.kiwi-electronics.com/nl/raspberry-pi-boards-behuizingen-uitbreidingen-en-accessoires-59
Mini PC with 6 GB RAM, 64 GB e-MMC is about $60.
OTOH I have 3 Ethernet switches in use, 2 USB hubs, and a HDMI switch to switch between some Raspberry outputs on my monitor,
all with wallwarts to power those,
plus a POE module..
One cheap PC does not do all those above things, the cost is not so much in the computers.. but what hangs from it here.
Some stuff I wrote:
https://panteltje.nl/panteltje/newsflex/download.html
Last time I checked the uptime of my Pi4 4GB (the one that records most stuff), it was almost 600 days.
Never a glitch, unless I pull the power plus, even then plenty time on UPS to switch mains to my 250 Ah lifepo4 battery pack
and the 2 kW pure sine wave 12 V to 230 V inverter.
https://panteltje.nl/pub/250_Ah_12V_to_230V_sinewave_IXXIMG_0796.JPG
I recently bought a few cheap Orange Pi-s and Milkv Duo-s.
But they are low end machines. Would be reasonably powerful
as desktop/server in 2000 (or maybe in 1999, clock freqency was >>>increasing fast in those years), but not now. I am using
Orange Pi-s to check that my software compiles fine on ARM.
I have Milkv Mars, which is slightly more powerful than Milkv Duo S,
I use it to test that my software compiles fine on Risc-V.
But otherwise those boards are useful as a way to control electronics
via Ethernet
Never used the orange-pi, I see:
https://www.newegg.com/p/3C6-06T4-000V0
Expensive?
Yes. That is very expensive variant. Also Newegg may be
expensive.
I bougt
aliexpress.com/item/1005005785695181.html
which is (including shipping) slightly more than $16.
Milkv-Duo S in $9 + shipping.
For HD video I have 3 HD satellite box receivers, 2 are connected to my Samsung TV.
Those show HD video and play and record HD from USB sticks and were about 35 Euro (40 USD?) each.
Some people claim that satellite box receivers can serve as cheap
computers, but I did not try.
--
Waldek Hebisch
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